Known photovoltaic cells comprise a semi-conductor body wherein light excites free charge carriers, which give rise to an output voltage and current between and through output terminals of the cell. The semi-conductor body is a thin flat sheet, with a large diameter and a much smaller thickness between its front and back surface. Electrodes distributed over substantially the entire front and back surface provide low resistance connections to the terminals. In many photovoltaic cells, the terminals are also provided on the front and back surface, together with the electrodes to which they are connected. However, it is also known to provide the terminals both on the same surface, typically on the back surface, that is, the surface that is turned away from the sun (or other light source) during use. Terminals on the same surface are made possible by a metal wrap through connection (MWT) in the form of a hole (also called via) filled with conductor material that runs from one surface to another.
The use of MWT connections has the problem that it can give rise to short circuits that may lead to loss of output current through the terminals or even damage. Since MWT connections were first proposed for photovoltaic cells, this problem has resulted in many proposals for avoiding short circuits. In spite of the long felt need for a solution to the short circuit problems of MWT in photovoltaic cells, the solutions are still quite complex in terms of additional processing and required accuracy.
A process of manufacturing photovoltaic cells with MWT connections is known from an article by Florian Clement et al, titled “Pilot Line processing of screen printed cs-Si MWT solar cells exceeding 17% efficiency”, published in the 34th IEEE PV Specialists conference, Philadelphia, 2009 pages 223-227. In this process, the starting point is a semiconductor substrate with vias through the substrate. A junction is realized by doping the surface. On the back surface, a back surface field layer (BSF) is created to provide contact to and passivation of the bulk. P contacts are also printed onto the back surface, which serve to realize one of the terminals of the cell. Conductor paste is printed on the front surface of the cell in the form of an electrode grid pattern that runs over the via. In order to provide a connection from the other terminal to the front, an area of conductor paste is first printed on the back surface at and around the location of the via and into the via. The conductor pastes are heated in a firing step, whereby electrodes are formed. The cell's output voltage can be coupled out from the back surface, between the P contacts and fired conductor paste.
Like all processes of manufacturing photovoltaic cells with MWT technology, this process requires additional measures to prevent short circuit problems involved with the via. Possible short circuit problems in this cell may involve unintended current paths in the wall of the via and currents due to local flaws in the emitter layer and alignment of cell features.
The process by Clement et al. addresses these problems by providing an emitter layer in the via, and locally on the rear in an area incorporating the location of the via and front contact, combined with cutting trenches in the front and back surface, for example by laser cutting. A trench is provided on the front surface near the edge of the cell to prevent current from the front surface around the edge. Furthermore, trenches are cut on the back surface in the local emitter area, encircling the areas of conductor paste on the back that are in contact with the vias. When the area of conductor paste is accurately aligned and trenches are properly positioned to separate the areas of (front-contacting) conductor paste from the BSF, this prevents a short circuit. The requirement of reliable application of the emitter layer on the wall of the hole limits the choice of available processes for applying the emitter. Due to process limitations complex measures are needed to apply this technique to n-type semi-conductor bodies.
US 2007/0023082 and EP1950810 describe a similar cell wherein a graded p-type emitter layer on the front surface of the n-type substrate is covered by a conducting coating that is electrically connected to a first electrode on the back surface through a via. On the back surface a graded n-type layer is used as a back surface field in contact with a second electrode, and a layer with an intrinsic-to-p-type grading is provided in an area incorporating the via. A trench separates the graded n-type layer from the layer with intrinsic-to-p-type grading and thus the parts of the back surface that are in contact with the first and second electrode. In another embodiment, the graded n-type layer may be selectively removed from the area incorporating the via, or deposited selectively outside that area and the contact electrode to the via is provided on the back surface on a simple intrinsic amorphous silicon layer.
In these embodiments the via contains a conductor which is electrically connected to the emitter, and because the via wall is not passivated or isolated, the emitter contact is therefore in direct contact with base material, a configuration which increases the risk of shunt or reverse current problems. US 2007/0023082 also mentions the possibility of first removing the graded n-type layer over the entire part of the back surface that is in contact with the first electrode. This reduces leakage, but it makes the manufacturing process more complex.